High temperature superconductor (HTS) materials provide a means for carrying extremely large amounts of current with extremely low loss. HTS materials lose all resistance to the flow of direct electrical current and nearly all resistance to the flow of alternating current when cooled below a critical temperature. The development of HTS wires (the expression “wires” is used here for a variety of conductors, including tape-like conductors) using these materials promises a new generation of high efficiency, compact, and environmentally friendly electrical equipment, which has the potential to revolutionize electric power grids, transportation, materials processing, and other industries. However a commercially viable product has stringent engineering requirements, which has complicated the implementation of the technology in commercial applications.
In the second generation HTS wire technology, currently under development, the HTS material is generally a polycrystalline rare-earth/alkaline-earth/copper oxide, e.g. yttrium-barium-copper oxide (YBCO). The current carrying capability of the HTS material is strongly related to its crystalline alignment or texture. Grain boundaries formed by the misalignment of neighboring crystalline HTS grains are known to form an obstacle to superconducting current flow, but this obstacle decreases with the increasing degree of alignment or texture. Therefore to make the material into a commercially viable product, e.g. an HTS wire, the HTS material must maintain a high degree of crystalline alignment or texture over relatively long distances. Otherwise, the superconducting current carrying capacity (critical current density) will be limited.
HTS materials can be fabricated with a high degree of crystallographic alignment or texture over large areas by growing a thin layer of the material epitaxially on top of a flexible tape-shaped substrate, fabricated so that it has a high degree of crystallographic texture at its surface. When the crystalline HTS material is grown epitaxially on this surface, the crystal alignment of the HTS material grows to match the texture of the substrate. In other words, the substrate texture provides a template for the epitaxial growth of the crystalline HTS material. Further, the substrate provides structural integrity to the HTS layer.
A substrate can be textured to provide a template that yields an epitaxial HTS layer with excellent superconducting properties such as high critical current density. Materials such as nickel, copper, silver, iron, silver alloys, nickel alloys, iron alloys, stainless steel alloys, and copper alloys can be used, among others. The substrate can be textured using a deformation process, such as one involving rolling and recrystallization annealing the substrate. An example of such a process is the rolling-assisted biaxially textured substrate (RABiTS) process. In this case large quantities of metal can be processed economically by deformation processing and annealing and can achieve a high degree of texture. Strips of metal as wide as, e.g., 4 cm have thus far been produced by this method, which can each then be slit into numerous smaller wires (e.g. 10 strips of 0.4 cm wires).
One or more buffer layers can be deposited or grown on the substrate surface with suitable crystallographic template on which to grow the HTS material. Buffer layers also can provide the additional benefit of preventing diffusion over time of atoms from the substrate material into the crystalline lattice of the HTS material or of oxygen into the substrate material. This diffusion, or “poisoning,” can disrupt the crystalline alignment and thereby degrade the electrical properties of the HTS material. Buffer layers also can provide enhanced adhesion between the substrate and the HTS layer. Moreover, the buffer layer(s) can have a coefficient of thermal expansion that is well matched to that of the superconductor material. For implementation of the technology in commercial applications, where the wire may be subjected to stress, this feature is desirable because it can help prevent delamination of the HTS layer from the substrate.
Alternatively, a non-textured substrate such as Hastelloy can be used, and textured buffer layers deposited by means such as the ion-beam-assisted deposition (IBAD) or inclined substrate deposition (ISD). Additional buffer layers may be optionally deposited epitaxially on the IBAD or ISD layer to provide the final template for epitaxial deposition of an HTS layer.
By using a suitable combination of a substrate and one or more buffer layers as a template, an HTS layer can be grown epitaxially with excellent crystal alignment or texture, also having good adhesion to the template surface, and with a sufficient barrier to poisoning by atoms from the substrate. The HTS layer can be deposited by any of a variety of methods, including the metal-organic deposition (MOD) process, metal-organic chemical vapor deposition (MOCVD), pulsed laser deposition (PLD), thermal or e-beam evaporation, or other appropriate methods. Lastly, a cap layer can be added to the multilayer assembly, which helps prevent contamination of the HTS layer from above. The cap layer can be, e.g., silver, and can be, e.g., sputtered onto the HTS layer. An exemplary multilayer HTS assembly includes a biaxially textured substrate of nickel with 5% tungsten alloy; sequentially deposited epitaxial layers of Y2O3, YSZ, and CeO2; epitaxial layer of YBCO; and a cap layer of Ag. Exemplary thicknesses of these layers are: a substrate of about 25-75 microns, buffer layers of about 75 nm each, a YBCO layer of about 1 micron, and a cap layer of about 1-3 microns. HTS wires as long as 100 m have been manufactured thus far using techniques such as those described above. In this assembly the bottom of the substrate can be considered the “back” of the assembly, and the top of the cap layer can be considered the “front.”
During use, it is desirable that the HTS wire is able to tolerate bend strains. A bend induces tensile strain on the convex outer surface of the bend, and compressive strain on the concave inner surface of the bend, thereby subjecting the HTS layer to tensile or compressive strains depending on the direction in which the wire is bent. While a modest amount of compressive stress can actually enhance the current carrying capacity of an HTS layer, in general subjecting the whole assembly to stress (especially repeated stress) places the wire at risk of mechanical damage. For example, cracks could be formed and propagate in the HTS layer, degrading its mechanical and electrical properties, or the different layers could delaminate from each other or from the substrate.
Methods for reducing stress in the HTS layer are described, e.g., in U.S. Pat. No. 6,745,059 and U.S. Pat. No. 6,828,507. For example, a copper strip, chosen to have similar thickness and mechanical features to the substrate, can be bonded onto the upper surface of the insert. This sandwiches the HTS layer roughly in the middle of the overall structure, so if the assembly is bent, the HTS layer is neither at the outer nor inner surface of the bend. Two of these assemblies can also be bonded together at their respective copper strips to form a single HTS wire assembly. In this case, the two substrates face outward, and the copper tapes are in the middle of the assembly. In this case the inclusion of a second assembly provides additional current carrying capacity; however, electrical contact to the HTS layers requires splicing the wire open, or partially removing one of the inserts in the contact section.
A further issue for coated conductor HTS wires is that of environmental contamination when the wire is in use. Environmental exposure can slowly degrade the electrical performance of HTS layers. Also, in the presence of cryogenic liquids such as liquid nitrogen in contact with the wire, the liquid can diffuse into pores within the wire, and on warming can form “balloons” that can damage the wire. Sealing the wire is desirable to prevent either environmental exposure of the HTS layers or penetration of the liquid cryogen into the wire. Seals for HTS assemblies are described in, e.g. U.S. Pat. No. 6,444,917.